1. Field of the Invention
The present invention relates to memory control and, particularly, to a memory control technique in a microcomputer.
2. Description of Related Art
Lower current consumption of electronic equipment is strongly demanded today for environmental consciousness and so on, and an attempt has been made to reduce the current consumption of a microcomputer incorporated in electronic equipment.
A technique disclosed in Japanese Unexamined Patent Application Publication No. 2007-193433 is described hereinafter with reference to FIG. 9. FIG. 9 corresponds to FIG. 1 of Japanese Unexamined Patent Application Publication No. 2007-193433. In a processor shown therein, a PC register 11 is a program counter and updates an address of an instruction to be executed at each cycle. The value of the PC register 11 is the address of the instruction to be executed, and the case where the instruction at the address exists in a cache memory 13 is a cache hit, and the case where it does not exist is a cache miss. In the case of the cache hit, an instruction decoder 15 decodes the instruction, and an execution device 16 executes an operation and updates the value of the PC register 11. In the case of the cache miss, on the other hand, the instruction indicated by the PC register 11 is downloaded from an external storage device 12 (memory) to the cache memory 13. Further, an instruction at a peripheral address is also downloaded to the cache memory 13 and cache replacement is performed.
At this time, a branch prediction device 14 performs a search to determine whether there is a branch instruction in the instruction for which the cache replacement has been performed. If there is a branch instruction, the branch prediction device 14 analyzes whether a branch destination instruction is the cache hit or the cache miss. If the analysis result shows that the branch destination instruction is the cache miss, the branch prediction device 14 performs cache replacement of the branch destination instruction and prepares for the future because the branch destination instruction is expected to exit in the external storage device 12. In this case, an operation waiting time occurs by access to the external storage device 12 upon cache replacement. The branch prediction device 14 calculates the time as a penalty and also calculates in how many cycles from the currently executed instruction the branch instruction will be issued, and sets a lower execution frequency of operation processing.
If, for example, the number of instructions to be executed until the branch instruction is issued is five and the penalty is twenty-five cycles, it is necessary to execute the five instructions within thirty cycles, thus reducing the execution frequency to ⅙. The power consumption of the processor is thereby reduced.
Further, with improvement in the function of small electronic equipment such as a portable terminal, a user program of a microcomputer incorporated therein is ever increasing. Accordingly, the size of a memory used in the microcomputer significantly increases, so that the power consumption of the memory forms an increasingly large proportion in the microcomputer.
Japanese Unexamined Patent Application Publication No. 10-283275 discloses a technique of reducing the current consumption of a microcomputer by lowering the current consumption of a memory.
The above technique monitors an address issued by a central processing unit (CPU), and sets the currently accessed memory bank only to a high power mode by activating it at a high power level and sets the other memory banks to a standby mode. This reduces the power consumption of the memory banks not being accessed, thereby reducing the power consumption of the whole memory and the microcomputer.